Senior Test Lead

Job Summary

We are looking for a hands-on Electrical Engineer (EE) to perform high-speed SerDes characterization, validation, and debug for AI silicon and systems. The ideal candidate has deep experience with PCIe Gen6 and high-speed Ethernet SerDes and is comfortable operating advanced signal-integrity and SerDes characterization equipment.

Responsibilities

• Perform SerDes electrical characterization, compliance testing, and debug.
• Characterize PCIe Gen6 and high-speed Ethernet interfaces across voltage, temperature, and operating conditions.
• Execute eye diagram, jitter, BER, margining, and signal-integrity measurements.
• Debug link-training, signal-integrity, and board/channel issues.
• Operate high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and compliance test equipment.
• Analyze characterization data and work with silicon, board, firmware, and validation teams to resolve issues.
• Develop and automate characterization flows and data collection where applicable.

Qualifications

• BS/MS in Electrical Engineering or equivalent experience.
• Strong hands-on experience with high-speed SerDes characterization and debug.
• Experience with PCIe Gen6 and high-speed Ethernet SerDes strongly preferred.
• Strong understanding of signal integrity, jitter, eye diagrams, BER, equalization, channel loss, and link margining.
• Hands-on experience with high-speed scopes, BERTs, VNAs, probes/fixtures, and SerDes compliance equipment.
• Experience with board-level signal-integrity debug and silicon bring-up.
• Experience with AI accelerators, CPUs/GPUs, server silicon, or other complex SoCs preferred.
• Python or other scripting experience for test automation and characterization analysis is a plus.

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.

Key Responsibilities

We are looking for a hands-on Electrical Engineer (EE) to perform high-speed SerDes characterization, validation, and debug for AI silicon and systems. The ideal candidate has deep experience with PCIe Gen6 and high-speed Ethernet SerDes and is comfortable operating advanced signal-integrity and SerDes characterization equipment.

Responsibilities

• Perform SerDes electrical characterization, compliance testing, and debug.
• Characterize PCIe Gen6 and high-speed Ethernet interfaces across voltage, temperature, and operating conditions.
• Execute eye diagram, jitter, BER, margining, and signal-integrity measurements.
• Debug link-training, signal-integrity, and board/channel issues.
• Operate high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and compliance test equipment.
• Analyze characterization data and work with silicon, board, firmware, and validation teams to resolve issues.
• Develop and automate characterization flows and data collection where applicable.

Qualifications

• BS/MS in Electrical Engineering or equivalent experience.
• Strong hands-on experience with high-speed SerDes characterization and debug.
• Experience with PCIe Gen6 and high-speed Ethernet SerDes strongly preferred.
• Strong understanding of signal integrity, jitter, eye diagrams, BER, equalization, channel loss, and link margining.
• Hands-on experience with high-speed scopes, BERTs, VNAs, probes/fixtures, and SerDes compliance equipment.
• Experience with board-level signal-integrity debug and silicon bring-up.
• Experience with AI accelerators, CPUs/GPUs, server silicon, or other complex SoCs preferred.
• Python or other scripting experience for test automation and characterization analysis is a plus.

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.

Skill Requirements

We are looking for a hands-on Electrical Engineer (EE) to perform high-speed SerDes characterization, validation, and debug for AI silicon and systems. The ideal candidate has deep experience with PCIe Gen6 and high-speed Ethernet SerDes and is comfortable operating advanced signal-integrity and SerDes characterization equipment.

Responsibilities

• Perform SerDes electrical characterization, compliance testing, and debug.
• Characterize PCIe Gen6 and high-speed Ethernet interfaces across voltage, temperature, and operating conditions.
• Execute eye diagram, jitter, BER, margining, and signal-integrity measurements.
• Debug link-training, signal-integrity, and board/channel issues.
• Operate high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and compliance test equipment.
• Analyze characterization data and work with silicon, board, firmware, and validation teams to resolve issues.
• Develop and automate characterization flows and data collection where applicable.

Qualifications

• BS/MS in Electrical Engineering or equivalent experience.
• Strong hands-on experience with high-speed SerDes characterization and debug.
• Experience with PCIe Gen6 and high-speed Ethernet SerDes strongly preferred.
• Strong understanding of signal integrity, jitter, eye diagrams, BER, equalization, channel loss, and link margining.
• Hands-on experience with high-speed scopes, BERTs, VNAs, probes/fixtures, and SerDes compliance equipment.
• Experience with board-level signal-integrity debug and silicon bring-up.
• Experience with AI accelerators, CPUs/GPUs, server silicon, or other complex SoCs preferred.
• Python or other scripting experience for test automation and characterization analysis is a plus.

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.

Other Requirements

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.