Senior Test Lead

Job Summary

Candidates with more than 8 years’ experience is mandatory.  Lead Silicon validation track for customer silicon programs. That includes planning verification and bring-up before tape-out, running the first days on the bench when silicon returns, and building repeatable coverage for high-speed interfaces and memory. Hire and develop the engineers who will perform these activities and be the technical point of contact when a board does not come up.

Key Responsibilities

• Lead end-to-end functional validation on SoC / ASIC programs: test strategy, pre-silicon execution on emulation or FPGA, first-silicon bring-up, and close-out against agreed criteria.
• Define bring-up checklists and coverage plans that design, firmware, and the lab can execute against.
• Debug across board, package, silicon, and firmware with standard lab tools (JTAG/DAP, protocol analyzers, memory exercisers, scopes).
• Build and reuse test content for interfaces and memory (for example PCIe, DDR/LPDDR/HBM, Ethernet, USB) rather than starting from zero on every program.
• Lead a mixed onsite and offshore team. 

Skill Requirements

• Experience in SoC or ASIC functional validation, spanning pre-silicon and post-silicon.
• At least one program completed end-to-end as the technical owner of validation: from a written plan, through first silicon, to a documented closure.
• Hands-on depth in at least two of: JTAG/debug ports, high-speed interface validation, DRAM/HBM bring-up, C or UVM test content.
• Ability to decide whether a fail belongs to board, package, die, or firmware, and explaining that decision to design and to the customer.

Other Requirements

Must have skills - SoC or ASIC functional validation

Good to have skills

• Led validation on PCIe 5/6, DDR5/LPDDR5X, or HBM3E.
• Custom silicon or merchant ASIC that went into a shipping system.
• Built a test library that was reused on a second program.
• Led distributed teams across customer sites and India or Eastern Europe.