Senior Test Lead - Design Validation
Job Summary
As part of the verification team, will be responsible for independently developing and maintaining leading-edge constrained-random verification environments and using them to drive functional correctness of innovative designs
Key Responsibilities
developing and maintaining leading-edge constrained-random verification environments
Skill Requirements
experience in ASIC/SoC verification with SV/UVM environments
- In-depth knowledge of verification flows
- Clear understanding of constrained random verification process, functional coverage, assertion methodology & philosophy
- Team player with excellent communication skills and the desire to take on diverse challenges
- Prior verification experience in one or more of the following domains is must:
- Ethernet; MAC/PCS; TCP/IP; Forwarding/Lookups
- High bandwidth datapath; Queuing/Dequeuing Algorithms
Other Requirements
nullSource: the employer's careers page. Last checked 2026-10-14. Posted 2026-10-13.