Senior Engineer (Level 1)- DFT
-Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
-Be responsible for a comprehensive DFT plan and drive the implementation.
-Work with DFT and cross functional teams
-Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering ServicesSource: the employer's careers page. Last checked 2026-10-19. Posted 2026-09-01.
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