Senior Design Lead - Allegro PCB

Job Summary

5-7 years of SI analysis experience.Responsible for Electrical and Signal Integrity aspects of the hardware platform and package requirements for SOC products. The position includes working across areas of platform, software/BIOS, SOC H/W and 1. BackgroundIntel requires an experienced Power Integrity (PI) engineering resource to support ongoing product execution activities. The resource is expected to contribute immediately with minimal ramp-up and training requirements. The engagement is intended to address near-term resource constraints resulting from internal hiring limitations.    

Scope of WorkThe selected resource will provide Power Integrity simulation and modeling services supporting package and board-level designs.  

Key Responsibilities

Perform Power Integrity (PI) simulationsConduct package and board layout power analysisExecute PIBOM analysisGenerate S-parameter modelsDevelop reusable PI modelsAnalyze simulation results and provide recommendationsGenerate engineering reports and supporting documentationCreate customer-facing engineering collateral where requiredSupport development of PIER and Platform Design Guide contentParticipate in technical discussions with Intel engineering teams

Skill Requirements

3. Required Technical SkillsMandatory SkillsPower Integrity (PI) analysis experienceHSPICECadence Sigrity PowerDCCadence PowerSIPackage power delivery analysisBoard power delivery analysisS-parameter generation and analysisSignal/Power simulation methodologyEngineering documentation and reporting

Preferred SkillsSemiconductor industry experienceCustomer platform design experienceExperience supporting CPU, package, or board development programsFamiliarity with Platform Design Guides

Other Requirements

4. Resource RequirementsExperience5+ years relevant Power Integrity experience preferredCapable of operating independently with minimal supervisionAble to onboard quickly and contribute immediately5. Work Location & Working ModelRequirementDetailsPreferred LocationMalaysiaWorking ArrangementOnsite PreferredCustomer InteractionRegular collaboration with Intel engineering teamsTravelNot anticipated