FPGA IP Design Engineer - Intern

Job Details:

Job Description:

Altera is hiring a FPGA IP Design Engineer - Intern! As modern FPGAs become increasingly like a SoC, Altera's IP Systems and Solutions Engineering (IPSS) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera's FPGA devices. These solutions are provided as highly configurable intellectual property IP cores that are fully integrated with Altera's software CAD tool, Quartus Prime. The IP Cores we develop include Memory Interfaces (such as DDR5, LPDDR5, or HBM), custom chip-to-chip interfaces for high-speed ADC/DAC tiles (for radar processing), and leading-edge transceiver interfaces (to enable Ethernet, PCIe, and other protocols).

Altera's IP cores provide configurable access to these high-speed, high-bandwidth interfaces, leveraging dedicated and specialized silicon subsystems in the FPGA. The constantly rising speed and complexity of memory devices, chip-to-chip, and transceiver interfaces presents a challenging design problem that requires system level knowledge of silicon, software, IP, and customer applications. As an IP Design Engineering Intern, you will work with a team of engineers to develop and verify state-of-the-art memory interface, chip-to-chip, or transceiver-based IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

Job Responsibilities:

Your specific responsibilities can include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for memory, chip-to-chip, or transceiver interfaces
• RTL development
• Device support and CAD tool integration
• Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)
• Hardware power-on and debug
• New product release and rollout support, customer technical support.

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.​

Estimated Salary Range: $95K – $100K CAD​

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We use artificial intelligence to screen, assess, or select applicants for the position.​ This posting is for an existing vacancy.​ Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.

Qualifications:

Minimum Qualifications

The candidate must be pursuing a Bachelor's Degree in computer engineering, electrical engineering, engineering science, computer science, mathematics, or similar and 3+ months of experience or coursework in one, or more, of the following:

• Software programming and/or scripting (e.g. C/C++, Python), digital logic, RTL design (e.g. SystemVerilog, Verilog, VHDL), or similar

Preferred Qualifications

• FPGA design experience, Experience with RTL simulation, timing closure, STA, Experience with Memory Interfaces.
  

Job Type:

Student / Intern (Fixed Term)

Shift:

Shift 1 (Canada)

Primary Location:

Toronto, Ontario, Canada

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.